As the density of semiconductor circuits in a device increase, the difficulties in processing these circuits also increase, this directly affecting the yield of these devices. One of the highest density circuits presently manufactured is the dynamic random access memory (DRAM) which can include at present up to 64 million memory cells in each device. In this type of device, a plurality of memory cells are arranged in an array of rows and columns. In order for this type of memory device to be functionally usable, all 64 million memory cells must be operational under specified operating conditions. If even a single cell fails, this results in the entire device failing.
In order to increase yield in semiconductor memories, redundant structures are provided on the device allowing replacement of defective portions of the device. This is typically facilitated through the use of some type of fuse programming. This allows replacement of sections of the memory array determined to be defective, such as a column, and also alteration of decoding circuitry. The altered decoding operates to avoid any defective portion of the memory array that is addressed, and instead actually addresses a replacement or redundant portion of the memory. Data is stored in the addressed redundant portion during a WRITE operation and retrieved therefrom during a READ operation.
One problem that has occurred as the density of the memory arrays have increased is failures that occur after the cell replacement and subsequent burn-in. Although the cell replacement results in a memory device that passes the test, subsequent burn-in and reliability testing results in a certain percentage of the devices failing. In the manufacturing process of the semiconductor memory, certain steps are taken to decrease the number of failed cells prior to cell replacement, since there are only a limited number of replacement cells provided on the device. One failure mechanism is high leakage current due to interface trap density. In order to lower the interface trap density and stabilize the operation of the device, the device is subjected to an annealing process (hereinafter referred to as "sinter"). This sinter operation is achieved in an atmosphere of hydrogen at a predetermined temperature for a predetermined duration of time, and typically occurs toward the end of the fabrication process. The effect of the sinter is a reduction of the interface trap density by hydrogen termination which allows hydrogen to be connected to dangling bonds which exist in the semiconductor-oxide (SiO.sub.2) boundary/and within crystal defects. Once this is done, certain cells which previously had leakage currents above the specified current level will now fall below that current level and will not have to be replaced. Thereafter, the integrated circuit is packaged and subjected to a reliability test. One problem that exists with this procedure is that, in certain marginal cells, the hydrogen termination that is provided during the sintering operation is broken during the reliability test. This leaved unterminated dangling bonds in the semiconductor-oxide boundary and crystal defects in the memory cell junction. This results in increased leakage current at a level higher than the specified level.
In general, interface traps have been discussed in the literature and can be produced in several different ways: (1) thermal oxidation in dry oxygen or steam, (2) plasma oxidation, (3) avalanche injection of electrons or holes into the SiO.sub.2, (4) the diffusion of metals such as chromium to the Si--SiO.sub.2 interface, and (5) the exposure of the MOS system to ionizing radiation. There are a number of ways to control interface trap densities, one of which is annealing or sinter. It has been reported in the literature, E. H. Nicollian and J. R. Brews, MOS Physics and Technology, Wylie Interscience Publication, pp. 778-787 and 822-824, which reference is incorporated herein by reference, that low temperature post-metallization anneal will cause changes in both the interface trap density and the oxide-fixed charge density. The value of the interface trap density can change with low temperature annealing by up to one order of magnitude. The key agent responsible for a reduction of the interface trap density is the transfer of hydrogen into or out of the oxide layer by performing the low temperature anneal in a hydrogen atmosphere. This low temperature anneal typically provides a connection of a hydrogen atom to a dangling bond. The chemistry by which interface traps are activated and annihilated by hydrogen is generally unknown, but it is believed that the hydrogen attaches to a dangling bond. Thereafter a sealing layer impervious to water and hydrogen, is deposited.
Before annealing, a steam-grown SiO.sub.2 layer has a typical interface trap density in the low 10.sup.11 cm.sup.-2 eV.sup.-1 range near mid-gap and a dry oxygen-grown SiO.sub.2 layer has a typical interface trap density in the low 10.sup.12 cm.sup.-2 eV.sup.-1 range near mid-gap. After either a low or high temperature anneal, the interface trap density will be in the low 10.sup.10 cm.sup.-2 eV.sup.-1 range near mid-gap. Some of the atomic hydrogen diffuses to the Si--SiO.sub.2 interface and chemically reacts with the interface traps, making them electrically inactive.
In general, the interface trap density distribution has been modeled as being produced by a distribution of bond angles or by stretched bonds at the silicon surface. Local strain or local non-stoichiometry at the Si--SiO.sub.2 interface could cause these bond distortions. At the interface, the Si and the SiO.sub.2 are bonded by an oxygen in a lattice configuration wherein distortion of the Si--O bond angle by as much as 30.degree. is expected to create energy levels near the silicon conduction band edge, while distortion of the Si--Si bond angles in the silicon tends to produce energy levels near the silicon valance band edge. A bond-stretching model utilizes a number of bonds, a Si--O bond at the interface of the plane that causes trap levels at the lower half of the bandgap, stretched Si--Si bonds which cause trap levels in the upper half of the gap, and silicon dangling bonds which produce trap levels near mid-gap. It is the silicon dangling bond that is replaced by a hydrogen termination. This hydrogen termination can be broken during the reliability test procedures, resulting in an increase in interface trap density and leakage current. Subsequently the device fails if it was a marginal device prior to the sinter operation.